Agastya Seth

Staff AI Engineer. Agentic systems, LLM evals, and AI infrastructure for chip design.

I build AI agents that do real engineering work. At Synopsys I lead agentic AI for hardware-assisted verification, where a single tool run can take a day and the agents have to plan, wait, recover, and report on their own.

Before that I wrote C++ geometry code at Cadence, built NLP systems, and did an M.S. at ASU on LLM safety and LLMs for hardware. I also play piano, mostly improvising.

Agastya Seth standing beside a silver Mercedes 300SL roadster
1

Selected work

  • Agents that run chip-design flows Synopsys · 2025 to now

    An orchestrator that dispatches task agents across 20 to 30 hour EDA runs, and an agent chat engine used by about 800 engineers a month.

  • Glucose estimation from wrist PPG ASU ACME Lab · 2025

    A conditional VAE that rebuilds motion-corrupted PPG before CNN and Transformer models predict blood glucose. It cut MAE from 29.6 to 25.0 mg/dL and recovered about 2,000 unusable records.

  • Reward alignment for text-to-video ASU · 2024

    Led bringing ReNO's reward-based noise optimization into Pyramid-Flow. It sharpens single-step image models but blurs hierarchical video ones, and the write-up explains why.

  • LLMs for hardware security and test ASU · ICCD 2025, DATE 2026

    Multi-agent LLMs that generate and detect synthetic hardware vulnerabilities, and a focus session on agentic test generation.

  • Evaluating LLM defenses ASU · Findings of ACL 2024

    A systematic look at how LLM safety defenses trade off real protection against over-refusing harmless requests.

  • Privacy-preserving ECG with RL ASU ACME × UC Irvine · COINS 2025

    A PPO agent that transforms ECG data to resist re-identification linkage attacks while keeping it accurate enough for classification.

2

Experience

Full resume
  1. Jun 2025 - Present

    Synopsys

    Staff AI Engineer, HAV R&D (Tech Lead, Agentic AI)

    Sunnyvale, CA
  2. Graduated May 2025

    Arizona State University

    M.S. Computer Science (GPA 4.0), Graduate Research Assistant, ACME Lab

    Tempe, AZ
  3. May 2024 - Aug 2024

    Cadence Design Systems

    Machine Learning Intern, Cerebrus R&D

    San Jose, CA
  4. Jul 2020 - Jul 2023

    Cadence Design Systems

    Software Engineer II, Quantus R&D

    Noida, India
  5. Aug 2020 - Sep 2021

    LiqVid / Shiv Nadar University

    NLP Research Scientist (part-time)

    Remote
  6. Jan 2020 - Jul 2020

    ViSenze

    Data Science Intern

    Singapore
  7. Graduated Jun 2020

    Shiv Nadar University

    B.Tech. Electronics and Communication Engineering, Minor in Mathematics

    Greater Noida, India
3

Publications

6 papers
  1. ICCD 2025

    MALLS: Multi-Agent LLMs for Synthetic Hardware Vulnerability Generation and Detection

  2. DATE 2026

    Focus Session: Do Agentic LLMs Change the Paradigm of Hardware Test Generation?

  3. ACL 2025

    UnSeenTimeQA: Time-Sensitive Question-Answering Beyond LLMs' Memorization

  4. Findings of ACL 2024
  5. COINS 2025

    REACT: RL-Based Adaptive ECG Anonymization and Privacy Threat Mitigation

  6. IEEE TCAD (under review)

    LLM-DATA: LLM-Aided Design and Test Automation for Rapid Circuit and Systems Development